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Vamsi Krishna, K.
- FPGA Implementation of High Speed Error Detection and Correction of Orthogonal Codes using Segmentation Method
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1 Department of ECE, K L University, Vaddeswaram, Guntur - 522502, Andra Pradesh, IN
2 Department of ECM, K L University, Vaddeswaram, Guntur - 522502, Andra Pradesh, IN
1 Department of ECE, K L University, Vaddeswaram, Guntur - 522502, Andra Pradesh, IN
2 Department of ECM, K L University, Vaddeswaram, Guntur - 522502, Andra Pradesh, IN
Source
Indian Journal of Science and Technology, Vol 9, No 30 (2016), Pagination:Abstract
Background: Our main objective is to improve the error detection and correction capability using orthogonal codes with high security and speed. Statistical Analysis: In order to achieve high speed and security for error detection and correction, we have used cryptography technique. The concept of segmentation is specifically used, as it gives highly secured signal and also reduces the time complexity. Previous study incorporates mapping technique for error detection and correction. Our proposed methodology uses two decoders in place of mapping at the receiver end. This eases the performance and decreases the clock pulses. Findings: The proposed technique will send the k-bit data to encoders and it gets converted into orthogonal codes. The data is then encrypted using encryptor which consists of LFSR. The data is then sent to the receiver and then original data is retrieved using the decoders at the receiver. The multiple bit error correction can be done up to (n/4-1) bits. Here we have compared the delays for 4-bit, 5-bit, 6-bit, 7-bit, 8-bit data. After comparing our technique with the previous study we have found out that the delay time is gradually reduced. Our proposed work is done in n/2+1 comparison, where n represents the bit length of orthogonal codes. Hence this technique achieves 100% multiple bit error detection and error correction rate in the received signal. This technique is simulated in Xilinx software and implement using Field Programmable Gate Array (FPGA). Application/Improvements: This technique can be used for efficient transmission of data in the networks. There is also a wide scope for improvement to limit the bandwidth.Keywords
Comparator, Error Detection and Correction, FPGA, LFSR, Orthogonal Codes.- Transfer Learning-Based Approach for Early Detection of Alzheimer’s Disease .
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1 no, IN
1 no, IN
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Artificial Intelligent Systems and Machine Learning, Vol 14, No 1 (2022), Pagination: 13 - 17Abstract
Alzheimer's disease is one of the world's main health concerns today. People with Alzheimer's disease who are diagnosed early have the best chance of receiving effective therapy. It's critical to catch the sickness as early as possible. Magnetic resonance imaging is one way to define Alzheimer's disease by finding structural abnormalities in the brain (MRI). We propose that machine learning, specifically trained convolutional neural networks (CNNs) with transfer learning capable of making predictions about similar brain imagery, can aid in early detection. CNN enables the extraction of MRI properties and classification as Alzheimer's disease or normal brain. We used the VGG19 architecture to categorize patients as having no signs of Alzheimer's disease or having signs of very mild, mild, or moderate Alzheimer's disease. Based on a transfer learning methodology, this method correctly classifies MRI images into four phases of Alzheimer's disease with an accuracy of 85 percent.Keywords
--Alzheimers Disease, Transfer Learning, VGG19, MRI, CNN.References
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